An embodiment of the present invention relates to the field of integrated circuits, and more particularly, to an approach for leakage current compensation.
Static random access memory (SRAM), which is designed to coexist on the same die as a high performance logic process, is increasingly susceptible to leakage in metal oxide semiconductor (MOS) devices. Continued scaling of device sizes to improve the performance of logic has resulted in a significant increase in leakage currents.
To achieve high density, SRAMs often include a large number of bit-cells in a single column, which is typically implemented with a pair of differential bit-lines. Such an SRAM relies on the development of a differential voltage on a selected bit-line pair in response to a memory read operation directed to the SRAM. To develop the differential voltage, the bit-lines are first pre-charged to the power supply rails and the particular bit-cell on the corresponding column is selected. The selected bit-cell then discharges one of the bit-lines, depending on the value stored in the selected cell, with a total bit-line capacitance CbI and a discharge current of Idrive.
Where N cells are in a column, the unselected Nxe2x88x921 cells contribute a leakage current of Nxe2x88x921 times a leakage current Ileak. For this example, the voltage differential between the bit-lines develops at the rate
dv/dt=(Idrivexe2x88x92(Nxe2x88x921)*Ileak)/CbIxe2x80x83xe2x80x83(Eqn. 1)
For higher leakage currents, (Nxe2x88x921)*Ileak may be large enough to be capable of discharging the other bit-line of the differential bit-line pair.
As can be seen from Equation 1, increasing leakage currents lead to a reduction in the rate of swing development and, in fact, may reach a point at which the leakage current completely swamps the drive current.
One approach to addressing this issue is to reduce the number of memory cells per column of memory, i.e. decrease the value of N in the above example. This solution, however, reduces array efficiency and leads to an increase in area for the SRAM. Other types of circuitry, including, for example, register files and certain types of domino logic, for example, may also be adversely affected by device leakage.